|
||
|
|
|
              |
|
 |
 |
|||||||||||
|
 |
|
|||||||||
By William Van Winkle |
|||||||||||
What's Hot With Intel In a word: Core. We don't need to rehash the deficiencies of NetBurst here. Suffice it to say that the dictates of heat and physics put a premature end to early Intel predictions about scaling to 10 GHz with energy densities equivalent to the surface of the sun (not as hot as the sun, as some writers have said). NetBurst topped out at a stock speed of 3.8 GHz, and even then just barely. Who could have guessed that Intel's future would claim its roots in the Pentium Pro? The major advance made with the Pentium Pro was its implementation of a holding buffer in which out-of-order instructions could be dynamically resorted for maximum efficiency. If the algorithms used to perform this resorting resulted in a conflict, wherein a bumped up instruction tries to access resources that would have been made available by a formerly previous instruction, then significant latencies could ensue. However, as the algorithms got smarter, the number of such delays dropped. By the time of the Pentium M, this out-of-order processing had improved remarkably, which is partly why the little mobile chip blew away everyone's performance expectations. Now, with Core, this "Smart Memory Architecture" has evolved to is highest level yet and, combined with Intel's use of substantially larger on-die cache sizes than AMD, explains much of how Intel's Core is able to trounce the latency benefits of AMD's integrated memory controller.
Serendipitously, the Pentium M was drawing awed praise right about the time when NetBurst criticism was starting to become serious. Intel knew that NetBurst's road map was headed for an abrupt end, and upon seeing that the Banias core could quickly scale beyond the performance of contemporary NetBurst processors, the decision was made to transition the entire mobile, desktop, and server lines to the new design. The result is today's Core architecture (not to be confused with the Core Duo, which did not use the Core architecture), comprised of the Xeon 5100 series (Woodcrest), desktop Core 2 Duo (Conroe) and Core 2 Duo Extreme Edition, and mobile Core 2 Duo (Merom). All of these parts are dual-core and utilize the exact same CPU die. The differences today simply boil down to core frequencies, bus speeds, the amount of shared L2 cache, and, in the case of Xeon, if the chip can be harnessed in a multi-CPU platform. As mentioned above, one of Core's key advances is that it shares a common L2 cache between both cores. Intel's redundantly named Advanced Smart Cache allows either core to access up to 100% of the L2 cache, and the amount of cache allocated to each core changes dynamically as needed. The cache bus was doubled to a 256-bit width, and cache prefetching algorithms have been improved. Again, the more efficiently Intel can get data into on-die cache before it is needed and then process that data without resorting to the latencies and congestion of the front-side bus, the better the overall performance. Speaking of performance, any Core discussion must address power consumption. With Intel melting in the midst of NetBurst criticisms, AMD took the opportunity to make "performance-per-watt" an industry catchphrase since its competing desktop and server chips were offering both faster results and lower power consumption. Today, Intel has turned the tables on AMD. Even in situations where AMD chips spec similar power usage, Intel's Core crushes its competitor on speed. Core achieves its stunning performance-per-watt figures by getting more work done in each clock cycle. Several factors contribute to this. Not only does Core utilize a shorter processing pipeline, but macro-op and micro-op fusion enable more data to get crunched at each pipeline stage. Many x86 commands, often called macro-ops, are divided into microinstructions (micro-ops) at the start of the processing pipeline and are then recombined at the other end. Part of the difficulty in this process is making sure that the decoder that recombines the instructions receives them in the proper order. The Pentium M debuted a feature called micro-ops fusion that ties two microinstructions from the same macro-op together in the appropriate order, thus letting the CPU handle them as one command. Core now adds macro-ops fusion to the mix, enabling two macro-ops to be fused into a single instruction and enhancing processing efficiency even more. Macro- and micro-ops fusion are largely why Core excels and saves power despite a shorter execution pipeline.
But there's more. On top of the Enhanced Intel SpeedStep (EIST) technology carried over from the Pentium M, Intel's Dynamic Power Coordination kills off the old concept of a processor being "on" or "off". There are now four levels of power savings for each CPU core: Halt, Stop Clock, Deep Sleep, and Enhanced Deeper Sleep. Cores within a CPU are monitored independently, and one can be in a sleep state saving power while the other is fully active. Moreover, there are zones within each core that can be powered down while other zones are operational. This happens on the scale of seconds or fractions of a second, not the usual minutes we're accustomed to with screen savers. The end result is dramatic savings that will generally show average power usage far below Intel's stated maximums—another pleasant break from the past. Circling back to our discussion of quad-core chips, it remains true that, on paper at least, AMD's quad-core design might outperform Intel's Kentsfield (desktop) and Clovertown (servers). The pinch of the front-side bus may at last start to strangle Intel's architecture, and the latencies added by two discrete cache blocks needing to determine which has what data won't help. However, it seems reasonable to expect that Intel will increase its bus speeds to at least 1,333 MHz, and a revised architecture with two FSBs dynamically shared externally, just as cache resources are shared internally, surely isn't far-fetched. Moreover, just as Paxville evolved into Woodcrest, Intel's plans are almost bound to migrate the "glued" approach of Kentsfield and Clovertown into a more deeply integrated "true" quad design in the following generation. The race for quad-core is a sprint right now, and if Intel can buy time with a glued solution as an intermediate play, then so be it. Ultimately, given that the efficiencies of adding threads diminish under most applications, the push into four and eight cores (and beyond) on a board may be more of an exercise in marketing for 2007 than anything else. Also, one parting caveat on Intel quad-core: We have it on good authority that the "BadAxe 2" motherboard, based on the 975 chipset, will support Kentsfield. But that implies that existing 975X boards of all stripes may be similarly incompatible (although 965-based options now coming online will work fine with quad-core). We just went through finding that some relatively recent boards, despite being socket compatible, would not accept Core-based processors. Now we may be headed for another flurry of compatibility issues in the late fourth and/or early first quarter. Customers who know that today's AM2 is future-upgradeable to quad-core Athlon should not make the same assumption about today's Socket 775 platforms. VIA's Power Play AMD isn't the only company feeling the pinch of Conroe. While trailing a distant third in the CPU market, VIA's C7 processor shouldn't be overlooked. Code-named "Esther," the C7 currently spans from 1.0 to 2.0 GHz, sports FSB speeds up to 800 MHz, and embeds 128K of both L1 and L2 cache. In terms of packaging, the original C7 mimicked the 479-pin socket of the Pentium M but used VIA's own electrical signaling. While we haven't attempted this in-house, others have found that the Pentium M and older C7s can both run on VIA platforms featuring the company's Flexi-Bus technology. This isn't a bad spin for those who want a low-end PC with a decent CPU upgrade path. More recently, though, VIA transitioned C7 to its own Intel-incompatible nanoBGA2 package. Like some of its larger counterparts, the C7 also supports no-execute (NX) bit technology as well as SSE2 and SSE3 instructions. The C7 also improves prefetching routines versus its C3 predecessor. But the shining spec on Esther's resume is her low power consumption. The highest-end 2.0 GHz part tops out at 20W max TDP. The 1.8 GHz C7 only reaches to 15W, and the 1.5 GHz C7 only brushes 12W (and averages, according to VIA, only 8W). These maximum numbers compare quite well against Yonah's 31W spec—so well that VIA maintains (prior to Core 2 Duo, at least) it offers the best performance per watt in the world. This becomes more persuasive when you add in that the C7 is built with a 90nm SOI process and yields a much smaller, cheaper to manufacture package. The end result is that VIA delivers very solid, affordable performance for environments running basic applications, particularly in small form factor designs and/or in situations where the advantages of VIA's PadLock Security Engine (which is based on AES encryption executed in CPU hardware) can come into play. "The value for resellers is that you're going to have motherboards and barebones systems based on C7 that are low-cost with very low power consumption," says VIA marketing manager Keith Kowal, "making them especially good for small office environments if you start adding up all those PC's power bills. So it comes down to low power, low heat, low noise, and low cost." The trouble for C7 is that recent power drops on Intel's and AMD's parts have strained VIA's performance-per-watt claims. Moreover, the combination of Core's performance leap and the corresponding landslide in Pentium price points have compressed C7's area of opportunity. This explains why, despite VIA's continuing popularity in the niche and hobbyist spaces, you're more likely to hear the company discussing embedded and UMPC opportunities rather than the desktop. Fortunately, the C7 also has a mobile counterpart, the C7-M, that holds more promise for resellers. The C7 and C7-M are essentially identical parts save that the C7-M adds some optimizations for power savings. More notably, VIA recently debuted an ultra-low voltage (ULV) version of the C7-M. The 1.5 GHz ULV part maxes at a mere 7.5W, half the power of the equivalent C7-M. The svelte form factors that should result from this will likely entice plenty of road warriors who do little beside office productivity and Web applications, and numbers posted on VIA Arena (www.viaarena.com) show the 1.5 GHz ULV showing markedly better battery runtime than an equivalent frequency Dothan Pentium M. "The C7-M enables low-cost notebooks that still have good performance, good battery life, and deliver a solid offering in the value mobile space," says VIA's Kowal. "The pricing here is equivalent to bottom of the barrel Celeron M notebooks, breaking the $500 price point depending on the model. I've seen as low as $400. But because the C7-M has the same kind of power saving feature set as the Pentium M, you get a low-cost notebook with very good battery life that stays very cool, as opposed to a lot of Celeron M notebooks, which don't have any of those enhanced kind of SpeedStep features, so the battery life isn't that great and they tend to run hot." The catch is that you may have to dig a bit to find VIA-based notebooks in the U.S. reseller channel. One to anticipate for Q4 will come courtesy of Everex. The unit should feature the C7-M along with 512MB of RAM, 60GB hard drive, DVD burner, wireless connectivity, and a 15.4" widescreen. Most impressive of all is the price: only $499 MSRP. The remaining Esther variant is the Eden processor line, presumably so named because they are fanless and thus beatifically quiet. All Eden processors use a 400 MHz FSB and VIA's 21mm x 21mm nanoBGA2 packaging, just like the standard C7. Regular Eden parts span from 400 MHz (2.5W max TDP) to 1.2 GHz (7W) while a special ULV pair of SKUs cover 1.0 GHz (3.5W) and 1.5 GHz (7.5W). For thin clients in particular, the Eden option can be particularly persuasive. ...more |
|||||||||||
 Back to top
|
|||||||||||
Copyright © 2007 RAM Magazine. All rights reserved.
Do not duplicate or redistribute in any form. |
|||||||||||
